System architecture
The QPIC-AI stack integrates photonic hardware, FPGA quantum processing, and AI-driven control into a unified autonomous QKD platform.
PIC-based QKD hardware
Thin-film lithium niobate (LiNbO₂) photonic integrated circuits form the optical front end of the QPIC-AI transmitter and receiver.
The PIC integrates electro-optic phase modulators, polarisation controllers, and on-chip thermal management to enable stable, high-bandwidth quantum state preparation and measurement.
Key design targets include sub-millisecond modulator switching, integrated power monitoring for loss stabilisation, and co-packaged driver electronics for a compact, deployable module form factor.
Key specifications
- Thin-film LiNbO₂ platform
- Phase + polarisation modulation
- On-chip thermal management
- Compact module form factor
FPGA-based QKD engine
The FPGA implements a complete phase-encoded BB84 QKD protocol stack, from raw qubit transmission through error correction and privacy amplification to final key output.
Real-time hardware interfaces connect the FPGA directly to the PIC module for modulator timing, photon counting synchronisation, and actuator control — all with deterministic latency.
The FPGA also hosts the AI inference engine (WP4), enabling tight integration between QKD performance monitoring and the autonomous correction loop.
Key specifications
- BB84 protocol full stack
- Real-time key distillation
- Deterministic hardware interfaces
- ETSI-aligned KMS interface
AI-assisted drift control
Lightweight neural network models are trained to predict drift in phase, polarisation, and thermal parameters from real-time sensor telemetry.
Models are quantised and compiled for FPGA deployment, maintaining inference latencies well below the target correction thresholds.
The closed-loop system continuously monitors QBER and raw key rate, triggering correction commands to PIC actuators when predicted drift exceeds learned thresholds.
Key specifications
- FPGA-deployed inference
- <5 ms phase/polarisation correction
- <200 ms thermal stabilisation
- <1 s auto-relock on link loss
KMS/SDN interoperability
QPIC-AI implements ETSI GS QKD 014 and 015 compliant key management interfaces, enabling integration with existing telecom and critical infrastructure orchestration layers.
SDN controller integration is validated in the Vienna and Seoul pilots, enabling dynamic path and key provisioning in QCI and telecom network contexts.
Standards alignment ensures the QPIC-AI system can be deployed alongside existing QKD equipment without protocol translation middleware.
Key specifications
- ETSI GS QKD 014/015
- SDN controller integration
- Multi-vendor interoperability
- Telecom + enterprise profiles